A Scalable Silicon Photonic M-ary PPM Transmitter Using Cascaded MZI Binary-Weighted Delay Architecture

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This silicon photonic transmitter employs a cascaded binary tree of MZI switches and binary-weighted delay lines to decouple modulator switching speeds from PPM slot durations. By shifting the complex timing logic from the electronic domain to the optical domain, the architecture enables scaling to high-order pulse position modulation without bandwidth-induced data rate bottlenecks. This facilitates significantly higher photon efficiency for long-range, deep-space optical communication links.